1. Field of the Invention
The present invention relates, in its more general aspect, to the field of the microelectronics with nanometric semiconductor electronic devices and to the field of the nano-manufacturing.
In particular, the invention relates to a hosting structure of nanometric components on parallel planes as it will be more apparent hereafter in the description, where it will be also simply indicated as nanometric structure.
Moreover, the invention relates to a manufacturing method of such a structure.
2. Description of the Related Art
As it is well known, in the field of the microelectronics the need of realizing circuit configurations of more and more reduced dimensions is particularly felt.
In the last thirty years, the progress of the electronic technology has followed a trend governed by that which is known as “Moore Law”, an empirical law stating that the capacity of storing information in memory devices doubles each eighteen months approximately, whereas the calculation performance of the CPUs (Central Processing Units) improve of a factor two each twenty-four months, as reported in the scheme of FIG. 1.
The Moore law is based on the capacity of reducing the geometries of the considered devices and it highlights how dimensions have passed from being equal to 2 μm for the eighties technologies, to being equal to 130 nm in 2001, to currently being equal to 90 nm.
However, the current technology is quickly reaching the physical limits of its possibilities and this implies a limitation in the reduction of the dimensions of the electronic devices which can be realized. In particular, the currently used photolithography processes are subject to drastic dimensional limitations for dimensional values being lower than 100 nm.
Forward techniques have thus been developed such as x-ray non-optic lithography, extreme ultra-violet lithography and the electronic beam lithography which allow to realize circuit configurations with dimensions in the order of some tenths of nanometres.
These techniques, however, require complex instruments characterized by excessively long times of lithographic etching and they thus result too expensive for being applied to a mass industrial manufacturing.
As an alternative, sub-lithographic patterning techniques have been developed based on controlled (conformable) deposition and of selective removal of a functional material on a suitable layer for realizing nanometric elements.
These techniques have allowed the adjustment of methods for realizing semiconductor substrates suitable for obtaining different typologies of components, as for example indicated in the U.S. Pat. Nos. 6,570,220 and 6,063,688 both to Doyle et al.
In particular, in these patents a deep submicrometric structure is described for transistors and, respectively, a relative method for realizing it. This method provides the realization, on a silicon substrate by means of lithography, of first spacers in a first material whereon, by means of controlled deposition, a layer of a second material is realized. Moreover the thickness of the layer of the second material is approximately half the width of the first spacers.
The selective removal of the second material, carried out by means of anisotropic etching, thus defines second spacers each being adjacent to respective side portions of the first spacers, and each having width equal to the thickness of the layer of this second material.
With a successive selective chemical etching the first spacers are removed, leaving on the surface of the semiconductor substrate only the second spacers. The deposition of a layer of a third material, controlled in the thickness, followed by a selective removal with anisotropic etching, defines third spacers.
These third spacers, each adjacent to respective side portions of the second spacers, have a length equal to the thickness of the layer of the third material. With a selective chemical etching the second spacers are removed leaving on the surface of the semiconductor solely the third spacers.
The operations of controlled depositions, of anisotropic etching and of selective etching are repeated more than once, for realizing spacers of reduced width of 100 Å or less, separated from one another by a distance of around 200 Å. By depositing, finally, some dielectric material in the region defined between two consecutive spacers, a conductive region is realized which can be used for realizing a CMOS transistor.
The above method needs, however, a preliminary and accurate programming since each realization step of an n order (with n>=1) of spacers is followed by a removal step of the spacers of a previous order (n−1), and it is thus necessary to provide a suitable distance and a suitable thickness of the first spacers for realizing last spacers of desired dimensions.
A different approach to the problem is given by the teaching indicated in the U.S. Pat. Nos. 6,128,214 and 6,314,019, both to Kuekes et al., wherein respectively a memory and communication system by means of nanometric wires arranged transversally on two levels is described. Such wires are joined in the intersections by bi-stable switches which take two different levels according to the potential difference between the respective two wires. Each switch is reconfigurable.
A further nanometric device is known from the U.S. patent application publication No. 2003/0206436 to Eaton et al., wherein memory devices are shown, in particular Flash memory devices wherein a plurality of transistors is realized by means of the intersection between first and second wires realized with semiconductor material. In particular, the first wires are used for realizing respective drain, source and channel regions and the second wires, alternatively realized also with metal, are used for defining the gate electrodes.
Although advantageous in several aspects, this solution results to be limited to the sole realization of memories of the Flash type.
As a matter of fact, in the last years, in the field of the microelectronics, in the perspective of a forward integration, the attention has been addressed towards the use of organic molecules capable of performing the vehicle or vector function for current transport.
For example, in U.S. Pat. No. 6,724,009, in the name of STMicroelectronics, S.r.l., the assignee of the present application, which patent is incorporated herein by reference in its entirety, a method for inserting in an electronic base component, such as a MOS or MOSFET transistor, organic molecules which can be activated as Schmitt trigger, is described.
This solution, although meeting the aim and advantageous for several aspects, needs a base component such as a MOS transistor which thus far has always remained in micrometric dimensions.